GPS FPGA Program Design

　　FPGA program mainly completes RF front-end control, USB chip interface control and generation of buffer FIFO to realize data transmission and control. The IF signal is first stored in the buffer area of the USB interface chip, and then sent to FX3 according to the data receiving clock of FX3. FX3 automatically completes the data transmission to the upper computer through a specific firmware program, and stores the received data through the upper computer software.

　　The FPGA program development environment is QUARTUS II, and Verilog HDL code is written. GPS and Beidou satellite signals are received respectively through SPI serial protocol configuration and setting parameters to realize IF data reception of various satellite signals. First, configure the RF front-end through sequential transmission, and set the serial input port to output 2-bit CMOS value from ADC. Each register has 28 bits and 4 address bits. During configuration, the data address is first, the serial data MSB is first, and the LSB is last.

　　After configuration of satellite IF signal output from RF front-end, FPGA converts 2-bit serial data into 16 bit parallel data via buffer and transmits it to USB parallel data bus. At the same time, Slave FIFO slave mode is used to control the read/write operation of USB chip, and the parallel data transmitted to endpoint FIFO is processed and then used by upper computer to complete storage and processing.

　　Firmware program mainly completes the initialization of CYUSB3014 chip, configures GPIF II interface as 32-bit synchronous Slave FIFO working mode, and external processor can read and write FX3 FIFO as common FIFO; Store the sampled and FPGA processed data into the FIFO buffer of CYUSB3014, send it to the host, receive and execute the instructions from the PC, and communicate with the FPGA through UART

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